Manufacturing method of array substrate and array substrate
US11018165B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Inventors
Key dates
| Filing date | Nov 6, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2203/04103
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of an array substrate and the array substrate are provided. The method comprises: forming an active layer on a substrate; forming an insulation layer on the active layer; forming a first metal layer on the insulation layer; forming an interlayer dielectric layer and a pixel electrode layer on the first metal layer by a same mask; forming a second metal layer on the interlayer dielectric layer, wherein the second metal layer comprises a source electrode, a drain electrode, and a touch signal line; and forming a patterned protective layer and a patterned common electrode layer on the second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.