Method and system for aging process on transistors in a display panel
US11018167B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 2, 2018 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Apr 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K71/831
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.