Reducing resource requirements for high-frequency counter arrays
US11018674B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/42
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and method include receiving counter update requests that are at a maximum frequency of fcounters; sending the counter update requests to a main block of counters that operate at a maximum frequency of fmain, where (fmain)≥(fcounters)/2; and responsive to a block of the main block of counters experiencing an overflow, sending corresponding counter update requests for the block of the main block of counters experiencing the overflow to a cache counter block that operates at a maximum frequency of fcache, where (fmain)≥(fcache) and (fcache)≥(fcounters)−(fmain). The counter update requests can be for Y×K total counters, and the main block of counters can include Y blocks of counters each block having K counters, Y and K are positive integers. (fmain)≥(fcounters)/2 ensures only one block of the main block of counters overflows simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.