Coarse delay lock estimation for digital DLL circuits
US11018676B2 · kind B2 · utility
1Cited by
4References
7Claims
0Family size
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Key dates
| Filing date | Apr 23, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.