Processor and chipset continuity testing of package interconnect for functional safety applications
US11022657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Mar 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/041
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.