Asymmetric data striping for uneven NAND defect distribution
US11023154B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 10, 2018 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device implements striping logic with respect to a plurality of slices, each slice including one or more storage media, such as NAND flash dies. Data operations are distributed among the slice in an unequal manner such that the frequency of selection of a slice decreases with number of defects in the NAND dies of that slice. For example, data operations may be distributed in a round-robin fashion with some slices being skipped periodically. In some embodiments, a skip map may be used that maps host addresses (HLBA) to a particular slice and device address (DLBA) in that slice, the skip map implementing the skipping of slices. The skip map may be smaller than the size of the storage device such that each HLBA is mapped to a zone of the storage device and a slice and offset within that zone are determined according to the skip map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.