Storage interface, timing control method, and storage system
US11023176B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Apr 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The storage interface includes a first programmable input/output unit configured to perform phase inversion on a clock signal that is output by the master controller, and output the phase-inverted clock signal to the storage device. The storage interface includes a second programmable input/output unit configured to delay a data signal that is output by the master controller, and output the delayed data signal to the storage device, where the delayed data signal is delayed by a time ΔT relative to the clock signal that is output by the master controller, and TCLK/2−ΔT≥TISU and ΔT≥TIH, where TCLK represents a period of the clock signal, TISU represents a shortest input setup time required by the storage device in each of different data rate modes, and TIH represents a shortest input hold time employed by the storage device in each of different data rate modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.