DRAM-based storage device and associated data processing method
US11023316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM-based storage device includes a DRAM and a control circuit. The DRAM includes a buffering area and a host accessing area. A data is stored in the host accessing area. The control circuit is electrically connected with the DRAM. The control circuit copies a portion of the data from the host accessing area to the buffering area at a predetermined time interval counted by the control circuit. Before the portion of the data is written to the buffering area, a first ECC decoding operation is performed on the portion of the data to correct error bits contained therein. If the portion of the data is corrected, the control circuit rewrites the corrected portion of the data into the host accessing area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.