Hybrid deferred assertion for circuit design
US11023637B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic simulation electronic design automation (EDA) application, the logic can be configured to receive a circuit design of an integrated circuit (IC) chip, the circuit design comprising an imported module comprising a list of simple immediate assertions (SIAs) for the imported module, wherein the circuit design comprises a first power domain and a second power domain, wherein the first power domain controls a power state of the second power domain and the imported module is assigned to the second power domain. The logic simulation EDA application can be configured to convert, in response to user input, each SIA in the list of SIAs into a respective hybrid deferred assertion (HDA) to form a list of HDAs for the imported module and execute a simulation of the IC chip, and execution of the simulation can include execution of a plurality of time slots for a plurality of simulation cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.