Memory array with reduced read power requirements and increased capacity
US11024348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.