Memory apparatus and method of controlling memory apparatus
US11024376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2018 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | May 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.