Bias techniques for controlled voltage distribution in stacked transistor amplifiers
US11025207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Sep 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.