Pipelined analog-to-digital converter
US11025262B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1009
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosure belongs to the field of integrated circuit technologies, and particularly relates to a pipelined analog-to-digital converter capable of correcting capacitor mismatch and inter-stage gain errors. According to the disclosure, a PN code is injected into a digital domain or an analog domain of a pipelined sub-analog-to-digital converter, a mean value of codes outputted by a sub-analog-to-digital converter of an (i+1)th pipeline stage in two cases that a PN code is equal to +1 and the PN code is equal to −1 is counted under the condition that a code outputted by a sub-analog-to-digital converter of an ith pipeline stage is b, and a capacitor mismatch error and an actual inter-stage gain of the ith pipeline stage are estimated according to the mean value and a relationship between a capacitor mismatch error and an actual inter-stage gain error of a previous pipeline stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.