Network interface for data transport in heterogeneous computing environments
US11025544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Jun 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.