Embedded logic analyzer and integrated circuit including the same
US11029357B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jun 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.