Apparatus and method for widened SIMD execution within a constrained register file
US11029960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2018 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Mar 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for widened SIMD execution on a limited register file. For example, one embodiment of an apparatus comprises: instruction dispatch circuitry to dispatch instructions of a thread for execution, including a first instruction to indicate a start of a double execution instruction sequence and a second instruction to indicate an end of a double execution instruction sequence; and execution circuitry including single instruction multiple data (SIMD) circuitry, the execution circuitry to execute the double execution instruction sequence in a first pass using a first set of lanes of the SIMD circuitry and to execute the double execution instruction sequence in a second pass following the first pass using a second set of lanes of the SIMD circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.