Non-volatile memory with double capa implant
US11031082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2020 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | May 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.