Silicon carbide stacked substrate and manufacturing method thereof
US11031238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2018 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/81
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.