Method for generating a bias current for biasing a differential pair of transistors and corresponding integrated circuit
US11031917B2 · kind B2 · utility
1Cited by
1References
26Claims
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Key dates
| Filing date | May 29, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jun 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operational amplifier integrated circuit includes a differential pair of transistors having a first input, a second input. A bias current generator applies a bias current to an output of the differential pair of transistors. A control loop generates a control voltage arising from a difference in potentials between the first input and the second input. An additional current that is added to the bias current is generated in response to the control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.