Enhancement mode startup circuit with JFET emulation
US11031933B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Dec 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/33523
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A startup circuit includes an enhancement mode transistor with a drain coupled to a startup circuit input, a source coupled to a first node, and a gate coupled to a second node. The startup circuit includes a current limiting circuit that controls a current path between the second node and a startup circuit output node based on a current sense voltage signal representing a current through the enhancement mode transistor, and a voltage regulation circuit controls a voltage of the second node to regulate a startup circuit output voltage of the startup circuit output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.