Apparatus and method for low-latency low-power analog-to-digital conversion with high input signals
US11031946B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2020 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Feb 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.