Scan-chain testing via deserializer port
US11035900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | May 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.