Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors
US11036276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Sep 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3296
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.