Integrated reliability, availability, and serviceability state machine for central processing units
US11036543B1 · kind B1 · utility
7Cited by
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19Claims
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Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Aug 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for an integrated reliability, availability, and serviceability (RAS) state machine are provided. Handling of RAS events by the Basic Input Output System (BIOS) of an integrated circuit device can result in lost processing time on the processing cores of a multi-core processor resulting from numerous system management interrupts generated by the BIOS. To reduce lost processing time, a dedicated state machine can execute instructions to handle RAS events independently of the BIOS and minimize the number of system management interrupts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.