Control processor unit (CPU) error detection by another CPU via communication bus
US11036573B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
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Key dates
| Filing date | May 16, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Sep 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A vehicle includes a first controller having a processor and a monitoring unit. The monitoring unit generates a question and transfers the question to the processor via a first bus. The processor generates an answer corresponding to the question and transfers the answer to the monitoring unit via the first bus. The processor transfers the question and the answer via a second bus. The vehicle includes a second controller coupled to the second bus and programmed to transition to a reduced performance mode responsive to the answer being different than an expected answer to the question.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.