Architectural enhancements for computing systems having artificial intelligence logic disposed locally to memory
US11036642B2 · kind B2 · utility
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4References
17Claims
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Key dates
| Filing date | Apr 26, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Apr 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.