Digital decoupling
US11036757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Mar 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/24565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This document described digital decoupling architectures that enable existing computing systems to run in parallel with new computing technologies. In some aspects, a method includes receiving, by a digital decoupling system and from a source computing system, one or more updated data sets that each include data that has been updated at the source computing system. A source data entry of a source table of a database of the digital decoupling system is updated based on each updated data set. In response to detecting the change to the source table, a target data entry that includes data of the updated source data entry is added to a target table of the database. An adapter module obtains the data of the target data entry and generates an event that specifies the data of the target data entry. The event is sent to one or more destination computing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.