Semiconductor device and dynamic logic circuit
US11037622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2018 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.