Memory controller, operating method of memory controller and memory system
US11037646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Jun 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.