Superconducting qubit with tapered junction wiring
US11038094B1 · kind B1 · utility
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Key dates
| Filing date | Jan 19, 2021 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Jan 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error correction can only work with superconducting qubits if qubit errors are lowered. Surface loss from thin oxides is currently a dominant error mechanism. Formulas for useful qubit geometries are presented to predict surface loss, which can be used to optimize the qubit layout. A significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss, as well as etching the underlying silicon to create free-standing wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.