Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
US11038666B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Dec 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for communication over a multi-wire, multiphase interface are disclosed. A clock recovery apparatus has a plurality of pulse generating circuits, a logic circuit and a delay flipflop. Each pulse generating circuit generates transition pulses in response to transitions in one of three difference signals representative of a difference in signaling state of a pair of wires in a three-wire bus. Transitions in the difference signals can occur at boundaries between sequentially-transmitted symbols. The first logic circuit may provide a single pulse in a combination signal at each boundary between pairs of symbols by combining one or more transition pulses. The delay flipflop is configured to respond to each pulse in the combination signal by changing signaling state of a clock signal that is output by the clock recovery apparatus. The symbols may be sequentially transmitted over the three-wire bus in accordance with a C-PHY protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.