Detecting irregularities in an input clock signal
US11042180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2020 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Mar 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus has an input interface for receiving an input clock signal, and a plurality N of clock divider circuits, each clock divider circuit generating a corresponding monitored clock signal by dividing the input clock signal by N. Each clock divider circuit is arranged, when generating a leading edge of each clock cycle of its corresponding monitored clock signal, to use a leading edge of a different clock cycle of the input clock signal to the clock cycle of the input clock signal used by any other of the clock divider circuits. Analysis circuitry provided in association with each clock divider circuit produces a width indication for each clock cycle of the corresponding monitored clock signal. Alarm generation circuitry then triggers an alarm signal when, for any of the monitored clock signals, a variation in the width indication is detected over multiple clock cycles of that monitored clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.