Circuit arrangement region failure prediction apparatus and method based on sensor output score
US11042431B2 · kind B2 · utility
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2References
16Claims
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Key dates
| Filing date | Apr 23, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Oct 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A failure prediction apparatus includes a memory and a processor coupled to the memory. The processor acquires a score based on an output of each of a plurality of sensors associated with each of a plurality of circuit arrangement regions, in each of the plurality of circuit arrangement regions a logic circuit constructed by programming is arrangeable, and performs a process of making a determination on a possibility of an occurrence of a failure with respect to each of the plurality of circuit arrangement regions based on the score for each of the circuit arrangement regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.