Communication between field programmable gate arrays
US11042497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2018 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Apr 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The implementations of the subject matter described herein relate to communication between field programmable gate arrays. In some implementations, an FPGA device comprises a first protocol stack configured to: receive, from a source application, a data transmitting request for a destination application; package the data transmitting request into a first packet by adding a header to the data transmitting request, the header indicating the source application and the destination application; and transmit a physical address of a second protocol stack connected with the destination application. The FPGA device further comprises a PCIe interface configured to: package the first packet into a second packet based on the physical address of the second protocol stack received from the first protocol stack so that the first packet serves as a data portion of the second packet, the second packet being a TLP conforming to the PCIe standard; and transmit the second packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.