Vector processing core shared by a plurality of scalar processing cores for scheduling and executing vector instructions
US11042502B2 · kind B2 · utility
1Cited by
8References
11Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 24, 2015 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jul 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation processing apparatus is provided. The operation processing apparatus includes a vector operator and cores. The vector operator processes a vector operation with respect to an instruction that uses the vector operation, and each core includes a scalar operator that processes a scalar operation with respect to an instruction that does not use the vector operation. The vector operator is shared by the cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.