Integrated circuit composite test generation
US11042681B1 · kind B1 · utility
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25References
20Claims
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Key dates
| Filing date | Mar 22, 2018 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jun 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mi . . . j states using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering MN*j combinations. Related apparatus, systems, techniques and articles are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.