Semiconductor package
US11043440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Sep 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface disposed to oppose the active surface, a heat dissipation member, disposed on the inactive surface of the semiconductor chip, having a plurality of holes and including a graphite-based material, an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member, disposed on the active surface of the semiconductor chip, including a redistribution layer electrically connected to the connection pad. 0<b<0.6a, in which “a” denotes a planar area of the heat dissipation member and “b” denotes a sum of planar areas of the plurality of holes on a plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.