Array substrate and display panel
US11043510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jun 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a display panel are proposed. Each of the signal conversion lines of the array substrate extends in the first direction, and connects two connection terminals adjacent to the each of signal conversion lines. Projections of the connection terminals on the reference plane in the second direction do not overlap. In this manner, the design that the adjacent connection terminals are interlaced can increase the spacing between the adjacent connection terminals, thus resolving the problem that the spacing between connection terminals on the array substrate is excessively small and short circuiting tends to happen when bonding to cause poor bonding in the related art.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.