Analog computer architecture for fast function optimization
US11043951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An analog circuit for solving optimization algorithms comprises three voltage controlled current sources and three capacitors, operatively coupled in parallel to the three voltage controlled current sources, respectively. The circuit further comprises a first inductor, operatively coupled in series between a first pair of the capacitors and the voltage controller current sources and a second pair of the capacitors and the voltage controller current sources. The circuit further comprises a second inductor, operatively coupled in series between the second pair of the capacitors and the voltage controller current sources and a third pair of the capacitors and the voltage controller current sources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.