System for digital cancellation of clock jitter induced noise in a gyroscope with provides better power effect
US11047686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Nov 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a digital gyroscope, the rate signal (including the quadrature) and the displacement signal of the drive part are sampled with an ADC. This displacement signal has the same frequency and phase as the quadrature signal that gets sampled in the rate channels. The displacement signal is sampled with the same clock as the rate signal resulting in the displacement signal having the same close-in phase noise folded into the signal band as the sampled quadrature in the rate signal. The sampled drive signal is subtracted from the sampled rate signal to eliminate the clock jitter induced noise in the rate signal. This relaxes the close-in phase noise requirement of the PLL and allows for a low power PLL implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.