Low power mode testing in an integrated circuit

US11047904B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Kumar Abhishek · Bee Cave, US
• Srikanth Jagannathan · Austin, US
• Thomas Henry Luedeke · Oberbergkirchen, DE
• Venkannababu Ambati · Austin, US
• Mark Shelton Cinque · Austin, US
• Joseph Wright · Ames, US

Key dates

• Filing date: Mar 5, 2019
• Grant date: Jun 29, 2021
• Expiry date: Apr 9, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/2882
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.