Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices
US11048509B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Nov 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Providing multi-element multi-vector (MEMV) register file access in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device includes a vector processor comprising multiple processing elements (PEs) communicatively coupled via a corresponding plurality of channels to a vector register file comprising a plurality of memory banks. The vector processor provides a direct memory access (DMA) controller that is configured to receive a plurality of vectors that each comprise a plurality of vector elements representing operands for processing a loop iteration. The DMA controller arranges the vectors in the vector register file such that, for each group of vectors to be accessed in parallel, vector elements for each vector are stored consecutively, but corresponding vector elements of consecutive vectors are stored in different memory banks of the vector register file. As a result, multiple elements of multiple vectors may be accessed with a single vector register file access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.