Technology to ensure sufficient memory type range registers to fully cache complex memory configurations
US11048626B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Feb 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods may provide for technology that detects a misalignment condition, wherein the misalignment condition includes a memory map being misaligned with a granularity of a register, automatically appends a protected range to the memory map, wherein the protected range eliminates the misalignment condition, and defines an operational characteristic of the memory map via the register. In one example, the protected range is a non-existent memory (NXM) range appended via a source address decoder (SAD) rule, the register is a memory type range register (MTRR), and the operational characteristic is a cache characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.