SoC chip and method for controlling bus access
US11048648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Dec 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SoC chip includes: a bus mechanism including at least one MPU; an OTP memory configured to store bus access control information; a mode configuring module connected to at least one MPU and the OTP memory, the mode configuring module being configured to read the bus access control information from the OTP memory when the SoC chip is in a boot mode, and configure the MPU using the bus access control information, and the mode configuring module being further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU. The bus access control information is stored by using the OTP memory, so that corresponding bus access control information may be written into the OTP memory according to requirements of various application scenarios, thereby being adapted to different application scenarios and having great flexibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.