Systems and methods for providing multiple memory channels with one set of shared address pins on the physical interface
US11048654B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Feb 28, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are provided to combine multiple channels in a multi-channel memory controller to save area and reduce power and cost. An apparatus may comprise a first memory controller configured to access a first channel using a first protocol, a second memory controller configured to access a second channel using a second protocol that is different from the first protocol and a physical interface coupled to the first memory controller and a second memory controller. The physical interface may comprise a set of pins for an address and command bus shared by the first memory controller and the second memory controller for the first memory controller and the second memory controller to send address or command to respective channels by time division multiplexing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.