System and method for use in design verification
US11048844B1 · kind B1 · utility
1Cited by
3References
16Claims
0Family size
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Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Jun 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for improved design verification for a data processing device when performing a logic simulation. The system identifies certain corresponding coverpoints at different points in results of a logic simulation for a design. Using coverage results obtained for the design, a merging of the results is performed for the certain corresponding coverpoints in the design. In the merged results, a coverpoint is considered as covered if at least one corresponding coverpoint is covered during the logic simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.