Mirrored pixel arrangement to mitigate column crosstalk
US11049457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Apr 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0233
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.