Memory device having hardware regulation training
US11049536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2019 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Oct 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory control unit and a write output clock device. The memory control unit is used to provide a write input clock and a first control value. The write output clock device produces a plurality of internal clocks based on the write input clock, and selects a target internal clock from the plurality of internal clocks, and further delays the target internal clock to become a write output clock to a memory unit based on the first control value. The memory unit produces a data signal based on the write output clock. The memory control unit identifies whether the write output clock meets the time-sequence requirements of the memory unit. If the time-sequence requirements are not met, the memory control unit changes the first control value and/or changes the selected target internal clock to change the write output clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.