Systems and methods for implementing redundancy for tile-based intelligence processing computing architecture
US11049586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.