Semiconductor device having a reduced pitch between lead-out wirings
US11049809B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2020 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Mar 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One semiconductor device includes first to fourth wirings disposed within a prescribed interval in a first direction, extending in a second direction, and arranged at a first pitch in the first direction, first to third lead-out wirings disposed within the prescribed interval in the first direction, extending in the second direction, and arranged at a second pitch in the first direction, a bridge part disposed between the first lead-out wiring, and the second lead-out wiring, and connected to the first lead-out wiring, and the second lead-out wiring, a first contact part in contact with at least one part of the bridge part, and a second contact part in contact with the third lead-out wiring. One of either the first lead-out wiring, or the second lead-out wiring is connected to the second wiring, and the third lead-out wiring is connected to the fourth wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.